I. Field of the Disclosure
The technology of the disclosure relates generally to Field-Effect Transistors (FETs), and more specifically to the layout of gate structures in FETs.
II. Background
Transistors are essential components in modern electronic devices. Large quantities of transistors are employed in integrated circuits (ICs) in many modern electronic devices. For example, components of modern electronic devices, such as central processing units (CPUs) and memory units, employ a large quantity of transistors for logic circuits and data storage.
In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has increased. This increase in functional density is achieved in part through continued efforts to scale down transistor cells in ICs (e.g., reducing the size of transistor nodes in order to place increasingly more transistor nodes into the same amount of space). Transistor cells can be scaled down by a reduction in gate width and/or channel length of transistor nodes therein, for example. Transistors cells can also be scaled down by reducing the size of an isolation structure isolating a transistor node therein from adjacent transistor cells. For example, a transistor cell that includes an isolation structure comprising a double diffusion break (DDB) can be scaled down by instead implementing a single diffusion break (SDB).
For example, FIG. 1 is a cross-section of a conventional Fin Field-Effect Transistor (FET) (FinFET) cell 100. The FinFET cell 100 includes a FinFET 102 that includes an active gate 104 of a width W1 (e.g., fourteen (14) or sixteen (16) nanometers (nm)). The FinFET 102 further includes source and drain epitaxial regions 108 and 110 grown on a substrate 112. The source and drain epitaxial regions 108 and 110 are located in respective source and drain columns 114 and 116. The source and drain epitaxial regions 108 and 110 may comprise an epitaxial growth of Silicon Germanium (SiGe) or Germanium (Ge), for example. The source and drain epitaxial regions 108 and 110 include source and drain implants 118 and 120, respectively, for providing a corresponding source or drain to each of the source and drain epitaxial regions 108 and 110. The source and drain implants 118 and 120 may be formed by ion implantation, for example. The FinFET 102 further includes source and drain contacts 122 and 124 for providing access to the source and drain epitaxial regions 108 and 110, respectively, and thus, for providing access to an active channel region 126 between the source and drain epitaxial regions 108 and 110 under the active gate 104. The drain contact 124 is isolated from the active gate 104 by a distance D1 and from a dummy gate 134 by a distance D2. The dummy gate 134 has a width indicated as W4 in FIG. 1. In the FinFET 102, the distances D1 and D2 are substantially similar. It is noted that for purposes of clarity, the epitaxial region 108 has been defined as a source epitaxial region 108, the implant 118 of the epitaxial region 108 has been defined as a source implant 118, the epitaxial region 110 has been defined as a drain epitaxial region 110, and the implant 120 of the epitaxial region 110 has been defined as a drain implant 120. However, the source/drain designations of these elements are an example and can be either designated as being for a source or a drain based on how the FinFET cell 100 is connected in the circuit, since the active channel region 126 has no intrinsic polarity.
The FinFET cell 100 further includes an SDB isolation structure 129 to provide isolation between the FinFET 102 and, for example, an adjacent FinFET cell (not shown). The SDB isolation structure 129 comprises an SDB 130 of a width W2. The SDB 130 may include a shallow trench isolation oxide, for example. The SDB isolation structure 129 further includes the dummy gate 134.
Under the configuration of the FinFET cell 100 described above, the FinFET cell 100 has a width W3 (i.e., the space occupied by a single FinFET cell in an array of cells) that depends, for example, on the width W1 of the active gate 104, a distance D3 between the active gate 104 and the dummy gate 134, and the width W2 of the SDB 130. Thus, the FinFET cell 100 can be scaled down by, for example, by reducing one or more of the width W1 of the active gate 104, the distance D3 between the active gate 104 and the dummy gate 134, or the width W2 of the SDB 130. However, scaling down the FinFET cell 100 in this manner may be limited by fabrication and performance considerations. For example, due to fabrication limitations and/or isolation requirements, reducing the distance D3 may place the drain epitaxial region 110 closer to the SDB 130. Thus, during fabrication, the epitaxial growth of the drain epitaxial region 110 may be uneven across a top surface 142 of the drain epitaxial region 110 due to a facet mismatch between a facet 140 of the drain epitaxial region 110 and a facet 144 of the SDB 130. In particular, the facet 140 of the drain epitaxial region 110 may not match the facet 144 of the SDB 130, thus hindering growth of the drain epitaxial region 110 near the facet 144 of the SDB 130. Accordingly, growth of the drain epitaxial region 110 near the facet 144 of the SDB 130 will be slower than the growth of the drain epitaxial region 110 away from the facet 144 of the SDB 130. This uneven growth is illustrated in FIG. 1 by the uneven top surface 142 of the drain epitaxial region 110. This uneven growth of the drain epitaxial region 110 may result in reduced gate control and increased sub-threshold current in the FinFET 102. In particular, during later formation of the source implant 118 and the drain implant 120 in the source and drain epitaxial regions 108 and 110, respectively, the drain implant 120 may be disposed deeper in the drain epitaxial region 110 than desired, and deeper than the source implant 118 in the source epitaxial region 108 by a source/drain implant margin 146. This results in the active channel region 126 that is lower in the substrate 112 than desired, and thus further from the active gate 104 than desired. Having the active channel region 126 further from the active gate 104 than desired can result in reduced gate control of the active channel region 126, and thus degraded performance of the FinFET 102. Furthermore, having the active channel region 126 further from the active gate 104 than desired can result in a lower voltage threshold than desired for the FinFET 102. This decreased voltage threshold increases sub-threshold current, as the active gate 104 may not be able to fully close the active channel region 126 during an “off” state of the FinFET cell 100, thus increasing power consumption and degrading performance.
Current leakage can also result based on the dummy gate 134 being located close to the drain epitaxial region 110 and the drain contact 124. As the pitch of the FinFET 102 is reduced, the distance between the dummy gate 134 and the drain epitaxial region 110 and the drain contact 124 may be reduced. For example, distance D2 may be reduced as pitch is reduced. This close proximity between the drain contact 124 and the dummy gate 134 may result in a potential leakage current path 148 through the dummy gate 134, thus also increasing power consumption and degrading performance of the FinFET 102.